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<a href="#nested-classes">Data Structures</a> &#124;
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx___s_pkt_data.html">XCsi2Tx_SPktData</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains the Short Packet information from the Generic Short Packet Register.  <a href="struct_x_csi2_tx___s_pkt_data.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx___config.html">XCsi2Tx_Config</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The configuration structure for CSI Controller.  <a href="struct_x_csi2_tx___config.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The <a class="el" href="struct_x_csi2_tx.html" title="The XCsi2Tx driver instance data. ">XCsi2Tx</a> driver instance data.  <a href="struct_x_csi2_tx.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Macros</h2></td></tr>
<tr class="memitem:gad58795e87b55fa4c2aea73405171341d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gad58795e87b55fa4c2aea73405171341d">XCSI2TX_H_</a></td></tr>
<tr class="memdesc:gad58795e87b55fa4c2aea73405171341d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#gad58795e87b55fa4c2aea73405171341d">More...</a><br/></td></tr>
<tr class="separator:gad58795e87b55fa4c2aea73405171341d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22c9436f428a8fc799706fb133cb07e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga22c9436f428a8fc799706fb133cb07e4">XCSI2TX_ENABLE</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga22c9436f428a8fc799706fb133cb07e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flag denoting enabling of CSI.  <a href="#ga22c9436f428a8fc799706fb133cb07e4">More...</a><br/></td></tr>
<tr class="separator:ga22c9436f428a8fc799706fb133cb07e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa5b4a62581a8f8fd68092c4d9f63c7fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gaa5b4a62581a8f8fd68092c4d9f63c7fe">XCSI2TX_DISABLE</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gaa5b4a62581a8f8fd68092c4d9f63c7fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flag denoting disabling of CSI.  <a href="#gaa5b4a62581a8f8fd68092c4d9f63c7fe">More...</a><br/></td></tr>
<tr class="separator:gaa5b4a62581a8f8fd68092c4d9f63c7fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9dfcb58942d4e840968868fc0decea38"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga9dfcb58942d4e840968868fc0decea38">XCSI2TX_MAX_LANES</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga9dfcb58942d4e840968868fc0decea38"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max Lanes supported by CSI.  <a href="#ga9dfcb58942d4e840968868fc0decea38">More...</a><br/></td></tr>
<tr class="separator:ga9dfcb58942d4e840968868fc0decea38"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaad964d27150f8888fdcde05db9f9ad18"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gaad964d27150f8888fdcde05db9f9ad18">XCSI2TX_MAX_VC</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:gaad964d27150f8888fdcde05db9f9ad18"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max number of Virtual Channels.  <a href="#gaad964d27150f8888fdcde05db9f9ad18">More...</a><br/></td></tr>
<tr class="separator:gaad964d27150f8888fdcde05db9f9ad18"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8f58282f5d1917ec080b9b210aad48a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga8f58282f5d1917ec080b9b210aad48a6">XCSI2TX_HW_H_</a></td></tr>
<tr class="memdesc:ga8f58282f5d1917ec080b9b210aad48a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#ga8f58282f5d1917ec080b9b210aad48a6">More...</a><br/></td></tr>
<tr class="separator:ga8f58282f5d1917ec080b9b210aad48a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac7a1f2d7c25c0f7238931c4941af0da8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gac7a1f2d7c25c0f7238931c4941af0da8">XCSI2TX_GSP_MASK</a>&#160;&#160;&#160;0x00000001F</td></tr>
<tr class="memdesc:gac7a1f2d7c25c0f7238931c4941af0da8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of GSPs can be safely written to GSP FIFO, before it goes full.  <a href="#gac7a1f2d7c25c0f7238931c4941af0da8">More...</a><br/></td></tr>
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Typedefs</h2></td></tr>
<tr class="memitem:gaaa39ebc6ffb192f283664d248374eae2"><td class="memItemLeft" align="right" valign="top">typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gaaa39ebc6ffb192f283664d248374eae2">XCsi2Tx_CallBack</a> )(void *CallBackRef, u32 Mask)</td></tr>
<tr class="memdesc:gaaa39ebc6ffb192f283664d248374eae2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Callback type for all interrupts defined.  <a href="#gaaa39ebc6ffb192f283664d248374eae2">More...</a><br/></td></tr>
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Enumerations</h2></td></tr>
<tr class="memitem:ga46a443dfffd8f26578ebaf2a6139b4f3"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga46a443dfffd8f26578ebaf2a6139b4f3">XCsi2Tx_LCStatus</a> { <a class="el" href="group__csi2tx.html#gga46a443dfffd8f26578ebaf2a6139b4f3ae2ab61672a5cb405cae8c9770e7e7710">XCSI2TX_LC_LESS_LINES</a> = 1, 
<a class="el" href="group__csi2tx.html#gga46a443dfffd8f26578ebaf2a6139b4f3a328322afaa225277614e41216fb55954">XCSI2TX_LC_MORE_LINES</a>
 }</td></tr>
<tr class="memdesc:ga46a443dfffd8f26578ebaf2a6139b4f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef defines the different errors codes for Line Count status for a Virtual Channel when Frame End Generation is enabled.  <a href="group__csi2tx.html#ga46a443dfffd8f26578ebaf2a6139b4f3">More...</a><br/></td></tr>
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Functions</h2></td></tr>
<tr class="memitem:gac9ea3e1e3c6a8ecc2f5074caca2e4c6b"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gac9ea3e1e3c6a8ecc2f5074caca2e4c6b">XCsi2Tx_CfgInitialize</a> (<a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *InstancePtr, <a class="el" href="struct_x_csi2_tx___config.html">XCsi2Tx_Config</a> *CfgPtr, UINTPTR EffectiveAddr)</td></tr>
<tr class="memdesc:gac9ea3e1e3c6a8ecc2f5074caca2e4c6b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the <a class="el" href="struct_x_csi2_tx.html" title="The XCsi2Tx driver instance data. ">XCsi2Tx</a> instance provided by the caller based on the given Config structure.  <a href="#gac9ea3e1e3c6a8ecc2f5074caca2e4c6b">More...</a><br/></td></tr>
<tr class="separator:gac9ea3e1e3c6a8ecc2f5074caca2e4c6b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a0232c79ceea489774863ec4cc3d9e0"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga5a0232c79ceea489774863ec4cc3d9e0">XCsi2Tx_Reset</a> (<a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga5a0232c79ceea489774863ec4cc3d9e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will do a reset of the IP.  <a href="#ga5a0232c79ceea489774863ec4cc3d9e0">More...</a><br/></td></tr>
<tr class="separator:ga5a0232c79ceea489774863ec4cc3d9e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7f455150c7e612ad6ddf0c052fff1f57"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga7f455150c7e612ad6ddf0c052fff1f57">XCsi2Tx_Activate</a> (<a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *InstancePtr, u8 Flag)</td></tr>
<tr class="memdesc:ga7f455150c7e612ad6ddf0c052fff1f57"><td class="mdescLeft">&#160;</td><td class="mdescRight">Thsi function will enable/disable the IP Core to start processing.  <a href="#ga7f455150c7e612ad6ddf0c052fff1f57">More...</a><br/></td></tr>
<tr class="separator:ga7f455150c7e612ad6ddf0c052fff1f57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga874801fd63ef703d0b8ec36379b743a7"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga874801fd63ef703d0b8ec36379b743a7">XCsi2Tx_Configure</a> (<a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga874801fd63ef703d0b8ec36379b743a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will configure the core with proper number of Active Lanes.  <a href="#ga874801fd63ef703d0b8ec36379b743a7">More...</a><br/></td></tr>
<tr class="separator:ga874801fd63ef703d0b8ec36379b743a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad74fa52c21a09573d7838c8ec469cb82"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gad74fa52c21a09573d7838c8ec469cb82">XCsi2Tx_GetShortPacket</a> (<a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *InstancePtr, <a class="el" href="struct_x_csi2_tx___s_pkt_data.html">XCsi2Tx_SPktData</a> *ShortPacketStruct)</td></tr>
<tr class="memdesc:gad74fa52c21a09573d7838c8ec469cb82"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will get the short packet received in the FIFO from the Generic Short Packet Register and fill up the structure passed from caller.  <a href="#gad74fa52c21a09573d7838c8ec469cb82">More...</a><br/></td></tr>
<tr class="separator:gad74fa52c21a09573d7838c8ec469cb82"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac3002b53f14fc92a2f9dbd70466fb54f"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gac3002b53f14fc92a2f9dbd70466fb54f">XCsi2Tx_IsActiveLaneCountValid</a> (<a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *InstancePtr, u8 ActiveLanesCount)</td></tr>
<tr class="memdesc:gac3002b53f14fc92a2f9dbd70466fb54f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function checks the validity of the active lanes parameter.  <a href="#gac3002b53f14fc92a2f9dbd70466fb54f">More...</a><br/></td></tr>
<tr class="separator:gac3002b53f14fc92a2f9dbd70466fb54f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1f42ddbe8c72819877271b1e2b1b2f66"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga1f42ddbe8c72819877271b1e2b1b2f66">XCsi2Tx_SetLineCountForVC</a> (<a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *InstancePtr, u8 VC, u16 LineCount)</td></tr>
<tr class="memdesc:ga1f42ddbe8c72819877271b1e2b1b2f66"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the Line Count for virtual Channel if Frame End Generation feature is enabled.  <a href="#ga1f42ddbe8c72819877271b1e2b1b2f66">More...</a><br/></td></tr>
<tr class="separator:ga1f42ddbe8c72819877271b1e2b1b2f66"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7aceee43ac75b5e2e7fb5c072e99543d"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga7aceee43ac75b5e2e7fb5c072e99543d">XCsi2Tx_GetLineCountForVC</a> (<a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *InstancePtr, u8 VC, u16 *LineCount)</td></tr>
<tr class="memdesc:ga7aceee43ac75b5e2e7fb5c072e99543d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the Line Count for virtual Channel if Frame End Generation feature is enabled.  <a href="#ga7aceee43ac75b5e2e7fb5c072e99543d">More...</a><br/></td></tr>
<tr class="separator:ga7aceee43ac75b5e2e7fb5c072e99543d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf7407d28ef78a246a921b758e837dd90"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_csi2_tx___config.html">XCsi2Tx_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gaf7407d28ef78a246a921b758e837dd90">XCsi2Tx_LookupConfig</a> (u32 DeviceId)</td></tr>
<tr class="memdesc:gaf7407d28ef78a246a921b758e837dd90"><td class="mdescLeft">&#160;</td><td class="mdescRight">Look up the hardware configuration for a device instance.  <a href="#gaf7407d28ef78a246a921b758e837dd90">More...</a><br/></td></tr>
<tr class="separator:gaf7407d28ef78a246a921b758e837dd90"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8c4f599fd297b0b87b7b5028bc59a1a4"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga8c4f599fd297b0b87b7b5028bc59a1a4">XCsi2Tx_SelfTest</a> (<a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga8c4f599fd297b0b87b7b5028bc59a1a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Runs a self-test on the driver/device.  <a href="#ga8c4f599fd297b0b87b7b5028bc59a1a4">More...</a><br/></td></tr>
<tr class="separator:ga8c4f599fd297b0b87b7b5028bc59a1a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafc4a705bd3a295ac372fa02eb578af4d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gafc4a705bd3a295ac372fa02eb578af4d">XCsi2Tx_IntrHandler</a> (void *InstancePtr)</td></tr>
<tr class="memdesc:gafc4a705bd3a295ac372fa02eb578af4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is the interrupt handler for the CSI2 Tx core.  <a href="#gafc4a705bd3a295ac372fa02eb578af4d">More...</a><br/></td></tr>
<tr class="separator:gafc4a705bd3a295ac372fa02eb578af4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4dd6f019a905c50bfa662e9823cf5b00"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga4dd6f019a905c50bfa662e9823cf5b00">XCsi2Tx_SetCallBack</a> (<a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *InstancePtr, u32 HandleType, void *Callbackfunc, void *Callbackref)</td></tr>
<tr class="memdesc:ga4dd6f019a905c50bfa662e9823cf5b00"><td class="mdescLeft">&#160;</td><td class="mdescRight">This routine installs an asynchronous callback function for the given HandlerType:  <a href="#ga4dd6f019a905c50bfa662e9823cf5b00">More...</a><br/></td></tr>
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<tr class="memitem:ga3ff13690fd3d7cbb9ef1b0b8bf579235"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga3ff13690fd3d7cbb9ef1b0b8bf579235">XCsi2Tx_GetIntrEnable</a> (<a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga3ff13690fd3d7cbb9ef1b0b8bf579235"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will get the interrupt mask set (enabled) in the CSI2 Tx core.  <a href="#ga3ff13690fd3d7cbb9ef1b0b8bf579235">More...</a><br/></td></tr>
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<tr class="memitem:ga2caa416a631b37b3414f3ebe811fb50e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga2caa416a631b37b3414f3ebe811fb50e">XCsi2Tx_IntrEnable</a> (<a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *InstancePtr, u32 Mask)</td></tr>
<tr class="memdesc:ga2caa416a631b37b3414f3ebe811fb50e"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will enable the interrupts present in the interrupt mask passed onto the function.  <a href="#ga2caa416a631b37b3414f3ebe811fb50e">More...</a><br/></td></tr>
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<tr class="memitem:gad54b9d4f661d683594d59fe7ab428962"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gad54b9d4f661d683594d59fe7ab428962">XCsi2Tx_IntrDisable</a> (<a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *InstancePtr, u32 Mask)</td></tr>
<tr class="memdesc:gad54b9d4f661d683594d59fe7ab428962"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will disable the interrupts present in the interrupt mask passed onto the function.  <a href="#gad54b9d4f661d683594d59fe7ab428962">More...</a><br/></td></tr>
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<tr class="memitem:ga40b9d2c4e3ac95c5a55c085ba0412304"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga40b9d2c4e3ac95c5a55c085ba0412304">XCsi2Tx_GetIntrStatus</a> (<a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga40b9d2c4e3ac95c5a55c085ba0412304"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will get the list of interrupts pending in the Interrupt Status Register of the CSI2 Tx core.  <a href="#ga40b9d2c4e3ac95c5a55c085ba0412304">More...</a><br/></td></tr>
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<tr class="memitem:ga60da0ba950424b0e90d2cf108eefed2c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga60da0ba950424b0e90d2cf108eefed2c">XCsi2Tx_InterruptClear</a> (<a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *InstancePtr, u32 Mask)</td></tr>
<tr class="memdesc:ga60da0ba950424b0e90d2cf108eefed2c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will clear the interrupts set in the Interrupt Status Register of the CSI2 Tx core.  <a href="#ga60da0ba950424b0e90d2cf108eefed2c">More...</a><br/></td></tr>
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<tr class="memitem:ga79fec6c8f14f43478aedaaaae040447e"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga79fec6c8f14f43478aedaaaae040447e">Csi2TxSelfTestExample</a> (u32 DeviceId)</td></tr>
<tr class="memdesc:ga79fec6c8f14f43478aedaaaae040447e"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function checks if the Max Lane count from the generated file matches the value present in the protocol configuration register.  <a href="#ga79fec6c8f14f43478aedaaaae040447e">More...</a><br/></td></tr>
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<tr class="memitem:gae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr>
<tr class="memdesc:gae66f6b31b5ad750f1fe042a706a4e3d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">The entry point for this example.  <a href="#gae66f6b31b5ad750f1fe042a706a4e3d4">More...</a><br/></td></tr>
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Interrupt Types for setting Callbacks</h2></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_HANDLER_WRG_LANE</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_HANDLER_GSPFIFO_FULL</b>&#160;&#160;&#160;2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_HANDLER_ULPS</b>&#160;&#160;&#160;3</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_HANDLER_LINEBUF_FULL</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_HANDLER_WRG_DATATYPE</b>&#160;&#160;&#160;5</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_HANDLER_UNDERRUN_PIXEL</b>&#160;&#160;&#160;6</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_HANDLER_LCERRVC0</b>&#160;&#160;&#160;7</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_HANDLER_LCERRVC1</b>&#160;&#160;&#160;8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_HANDLER_LCERRVC2</b>&#160;&#160;&#160;9</td></tr>
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<tr class="memitem:gaeba76537f34ec4d0b563c28ad9aab71a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaeba76537f34ec4d0b563c28ad9aab71a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_HANDLER_LCERRVC3</b>&#160;&#160;&#160;10</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Device registers</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpe905567f3f1e4630e21d2f8192509576"></a>Register sets of MIPI CSI2 Tx Core </p>
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<tr class="memitem:ga946323f75e230f56d7fc2a9640bd8ab1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga946323f75e230f56d7fc2a9640bd8ab1">XCSI2TX_CCR_OFFSET</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:ga946323f75e230f56d7fc2a9640bd8ab1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Configuration Register.  <a href="#ga946323f75e230f56d7fc2a9640bd8ab1">More...</a><br/></td></tr>
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<tr class="memitem:gabb3185c624bf861b9d97e8dad49b3d48"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabb3185c624bf861b9d97e8dad49b3d48"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_OFFSET</b></td></tr>
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<tr class="memitem:ga9367d74644fe257d2d9ef283bf81d327"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga9367d74644fe257d2d9ef283bf81d327">XCSI2TX_GIER_OFFSET</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga9367d74644fe257d2d9ef283bf81d327"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Register.  <a href="#ga9367d74644fe257d2d9ef283bf81d327">More...</a><br/></td></tr>
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<tr class="memitem:gab2d607c7c70706cdb08326d2f9d35396"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gab2d607c7c70706cdb08326d2f9d35396">XCSI2TX_ISR_OFFSET</a>&#160;&#160;&#160;0x00000024</td></tr>
<tr class="memdesc:gab2d607c7c70706cdb08326d2f9d35396"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status Register.  <a href="#gab2d607c7c70706cdb08326d2f9d35396">More...</a><br/></td></tr>
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<tr class="memitem:ga2e9aa73ddca76ee93a3c18573a082f19"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga2e9aa73ddca76ee93a3c18573a082f19">XCSI2TX_IER_OFFSET</a>&#160;&#160;&#160;0x00000028</td></tr>
<tr class="memdesc:ga2e9aa73ddca76ee93a3c18573a082f19"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enable Register.  <a href="#ga2e9aa73ddca76ee93a3c18573a082f19">More...</a><br/></td></tr>
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<tr class="memitem:ga98c70dd97a33a24cd5a1d80f9fe9d902"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga98c70dd97a33a24cd5a1d80f9fe9d902">XCSI2TX_SPKTR_OFFSET</a>&#160;&#160;&#160;0x00000030</td></tr>
<tr class="memdesc:ga98c70dd97a33a24cd5a1d80f9fe9d902"><td class="mdescLeft">&#160;</td><td class="mdescRight">Generic Short Packet Entry.  <a href="#ga98c70dd97a33a24cd5a1d80f9fe9d902">More...</a><br/></td></tr>
<tr class="separator:ga98c70dd97a33a24cd5a1d80f9fe9d902"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga71d1e5d100d088c2482482878f868530"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga71d1e5d100d088c2482482878f868530">XCSI2TX_LINE_COUNT_VC0</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga71d1e5d100d088c2482482878f868530"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count for VC0.  <a href="#ga71d1e5d100d088c2482482878f868530">More...</a><br/></td></tr>
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<tr class="memitem:ga0416b10b41b6db1ec5a6ee91a79e7005"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga0416b10b41b6db1ec5a6ee91a79e7005">XCSI2TX_LINE_COUNT_VC1</a>&#160;&#160;&#160;0x00000044</td></tr>
<tr class="memdesc:ga0416b10b41b6db1ec5a6ee91a79e7005"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count for VC1.  <a href="#ga0416b10b41b6db1ec5a6ee91a79e7005">More...</a><br/></td></tr>
<tr class="separator:ga0416b10b41b6db1ec5a6ee91a79e7005"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga62f584b06977c2aaa760aebee9ca4545"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga62f584b06977c2aaa760aebee9ca4545">XCSI2TX_LINE_COUNT_VC2</a>&#160;&#160;&#160;0x00000048</td></tr>
<tr class="memdesc:ga62f584b06977c2aaa760aebee9ca4545"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count for VC2.  <a href="#ga62f584b06977c2aaa760aebee9ca4545">More...</a><br/></td></tr>
<tr class="separator:ga62f584b06977c2aaa760aebee9ca4545"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga23a3d797b27784997c641c8c8f0e984a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga23a3d797b27784997c641c8c8f0e984a">XCSI2TX_LINE_COUNT_VC3</a>&#160;&#160;&#160;0x0000004C</td></tr>
<tr class="memdesc:ga23a3d797b27784997c641c8c8f0e984a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count for VC3.  <a href="#ga23a3d797b27784997c641c8c8f0e984a">More...</a><br/></td></tr>
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<tr class="memitem:ga0de178a0d328d77c92f84bfa9eea9432"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0de178a0d328d77c92f84bfa9eea9432"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_GSP_OFFSET</b>&#160;&#160;&#160;0x00000078	/* &lt; GSP Status*/</td></tr>
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Bitmasks and offsets of XCSI_GIER_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpb5e847c8d19305532db4886d1c1fec20"></a>This register contains the global interrupt enable bit. </p>
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<tr class="memitem:gac6230fca4f7c1adbda9fe1552ef4b3d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gac6230fca4f7c1adbda9fe1552ef4b3d2">XCSI2TX_GIER_GIE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gac6230fca4f7c1adbda9fe1552ef4b3d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Enable bit.  <a href="#gac6230fca4f7c1adbda9fe1552ef4b3d2">More...</a><br/></td></tr>
<tr class="separator:gac6230fca4f7c1adbda9fe1552ef4b3d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga933b9901187f38c45f7b70e52e3344a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga933b9901187f38c45f7b70e52e3344a3">XCSI2TX_GIER_GIE_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga933b9901187f38c45f7b70e52e3344a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for Global Interrupt Enable.  <a href="#ga933b9901187f38c45f7b70e52e3344a3">More...</a><br/></td></tr>
<tr class="separator:ga933b9901187f38c45f7b70e52e3344a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga959e1d8eac158a90fdd7924124bf2bcc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga959e1d8eac158a90fdd7924124bf2bcc">XCSI2TX_GIER_SET</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga959e1d8eac158a90fdd7924124bf2bcc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the Global Interrupts.  <a href="#ga959e1d8eac158a90fdd7924124bf2bcc">More...</a><br/></td></tr>
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<tr class="memitem:ga4eee0cf8e8f3042e85023c2c9e614704"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga4eee0cf8e8f3042e85023c2c9e614704">XCSI2TX_GIER_RESET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga4eee0cf8e8f3042e85023c2c9e614704"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the Global Interrupts.  <a href="#ga4eee0cf8e8f3042e85023c2c9e614704">More...</a><br/></td></tr>
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Bitmasks and offsets of XCSI_CCR_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp7c29d0c6d8bba80908f37eecd1101400"></a>This register is used for the enabling/disabling and resetting the core of CSI2 Tx Controller </p>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CCR_COREENB_MASK</b>&#160;&#160;&#160;0x00000001 /* Enable/Disable core */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CCR_SOFTRESET_MASK</b>&#160;&#160;&#160;0x00000002 /* Soft Reset the core */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CSR_RIPCD_MASK</b>&#160;&#160;&#160;0x00000004 /* Core ready */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CCR_ULPS_MASK</b>&#160;&#160;&#160;0x00000008 /* ULPS */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CCR_CLKMODE_MASK</b>&#160;&#160;&#160;0x00000010 /* Clock Mode */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CCR_COREENB_SHIFT</b>&#160;&#160;&#160;0 	/* Shift bit for Core Enable*/</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CCR_SOFTRESET_SHIFT</b>&#160;&#160;&#160;1 	/* Shift bit for Soft reset */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CSR_RIPCD_SHIFT</b>&#160;&#160;&#160;2 	/* Bit Shift for Core Ready */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CCR_ULPS_SHIFT</b>&#160;&#160;&#160;3 	/* Shift bits for ulps */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CCR_CLKMODE_SHIFT</b>&#160;&#160;&#160;4 	/* Shift bits for clock mode */</td></tr>
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Bitmasks and offset of XCSI2TX_PCR_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpe2d68b6ea4d32ca6ea4ef4928363eddb"></a>This register reports the number of lanes configured during core generation and number of lanes actively used. </p>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_LINEGEN_MASK</b>&#160;&#160;&#160;0x00008000 /* Line generation Mode */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_PIXEL_MASK</b>&#160;&#160;&#160;0x00006000 /* Pixel Mode */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_MAXLANES_MASK</b>&#160;&#160;&#160;0x00000018 /* Maximum lanes in core */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_ACTLANES_MASK</b>&#160;&#160;&#160;0x00000003 /* Active  lanes in core */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_LINEGEN_SHIFT</b>&#160;&#160;&#160;15 	/* Line generation */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_PIXEL_SHIFT</b>&#160;&#160;&#160;13 	/* Pixel Mode */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_MAXLANES_SHIFT</b>&#160;&#160;&#160;3 	/* Max Lanes */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_ACTLANES_SHIFT</b>&#160;&#160;&#160;0 	/* Active Lanes */</td></tr>
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BitMasks interrupts</h2></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_IER_ALLINTR_MASK</b>&#160;&#160;&#160;0x0000003F /* All interrupts mask */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_ISR_ALLINTR_MASK</b>&#160;&#160;&#160;0x0000003F /* All interrupts mask */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_UNDERRUN_PIXEL_MASK</b>&#160;&#160;&#160;(1&lt;&lt;0)	/* Underrun Pixel */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_WRONG_DATATYPE_MASK</b>&#160;&#160;&#160;(1&lt;&lt;1)	/* Wrong data type */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_LINE_BUFF_FULL_MASK</b>&#160;&#160;&#160;(1&lt;&lt;2)	/* Line buffer full */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_DPHY_ULPS_MASK</b>&#160;&#160;&#160;(1&lt;&lt;3)	/* Dphy ulps */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI_GPSFIFO_MASK</b>&#160;&#160;&#160;(1&lt;&lt;4)	/* GPS fifo full */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI_INCORT_LANE_MASK</b>&#160;&#160;&#160;(1&lt;&lt;5)	/* Wrong lane configuration */</td></tr>
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<tr class="memitem:ga0044b3d448765635208740af525b7f8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga0044b3d448765635208740af525b7f8f">XCSITX_LCSTAT_VC0_IER_MASK</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:ga0044b3d448765635208740af525b7f8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC0 IER.  <a href="#ga0044b3d448765635208740af525b7f8f">More...</a><br/></td></tr>
<tr class="separator:ga0044b3d448765635208740af525b7f8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a70be53ce33122f5cc5d0f4d0450bf6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga5a70be53ce33122f5cc5d0f4d0450bf6">XCSITX_LCSTAT_VC1_IER_MASK</a>&#160;&#160;&#160;(1&lt;&lt;10)</td></tr>
<tr class="memdesc:ga5a70be53ce33122f5cc5d0f4d0450bf6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC1 IER.  <a href="#ga5a70be53ce33122f5cc5d0f4d0450bf6">More...</a><br/></td></tr>
<tr class="separator:ga5a70be53ce33122f5cc5d0f4d0450bf6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaffcbe2e0effcbd2ff9806e9e28ebf26"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gaaffcbe2e0effcbd2ff9806e9e28ebf26">XCSITX_LCSTAT_VC2_IER_MASK</a>&#160;&#160;&#160;(1&lt;&lt;12)</td></tr>
<tr class="memdesc:gaaffcbe2e0effcbd2ff9806e9e28ebf26"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC2 IER.  <a href="#gaaffcbe2e0effcbd2ff9806e9e28ebf26">More...</a><br/></td></tr>
<tr class="separator:gaaffcbe2e0effcbd2ff9806e9e28ebf26"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0bd1beb0451ef2e16f517a7933069e68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga0bd1beb0451ef2e16f517a7933069e68">XCSITX_LCSTAT_VC3_IER_MASK</a>&#160;&#160;&#160;(1&lt;&lt;14)</td></tr>
<tr class="memdesc:ga0bd1beb0451ef2e16f517a7933069e68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC3 IER.  <a href="#ga0bd1beb0451ef2e16f517a7933069e68">More...</a><br/></td></tr>
<tr class="separator:ga0bd1beb0451ef2e16f517a7933069e68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga10a735a664b23493bbcfe038e7fc5090"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga10a735a664b23493bbcfe038e7fc5090">XCSITX_LCSTAT_VC0_IER_OFFSET</a>&#160;&#160;&#160;(8)</td></tr>
<tr class="memdesc:ga10a735a664b23493bbcfe038e7fc5090"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC0 IER Offset.  <a href="#ga10a735a664b23493bbcfe038e7fc5090">More...</a><br/></td></tr>
<tr class="separator:ga10a735a664b23493bbcfe038e7fc5090"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3edc584a66bd4eec9e3d7f9527688719"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga3edc584a66bd4eec9e3d7f9527688719">XCSITX_LCSTAT_VC1_IER_OFFSET</a>&#160;&#160;&#160;(10)</td></tr>
<tr class="memdesc:ga3edc584a66bd4eec9e3d7f9527688719"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC1 IER Offset.  <a href="#ga3edc584a66bd4eec9e3d7f9527688719">More...</a><br/></td></tr>
<tr class="separator:ga3edc584a66bd4eec9e3d7f9527688719"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4b50b90be1a5046ac8620ce35a8316e0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga4b50b90be1a5046ac8620ce35a8316e0">XCSITX_LCSTAT_VC2_IER_OFFSET</a>&#160;&#160;&#160;(12)</td></tr>
<tr class="memdesc:ga4b50b90be1a5046ac8620ce35a8316e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC2 IER Offset.  <a href="#ga4b50b90be1a5046ac8620ce35a8316e0">More...</a><br/></td></tr>
<tr class="separator:ga4b50b90be1a5046ac8620ce35a8316e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga751e5c1a5b8ba04269280f5006b5b4e9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga751e5c1a5b8ba04269280f5006b5b4e9">XCSITX_LCSTAT_VC3_IER_OFFSET</a>&#160;&#160;&#160;(14)</td></tr>
<tr class="memdesc:ga751e5c1a5b8ba04269280f5006b5b4e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC3 IER Offset.  <a href="#ga751e5c1a5b8ba04269280f5006b5b4e9">More...</a><br/></td></tr>
<tr class="separator:ga751e5c1a5b8ba04269280f5006b5b4e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga142de52fd9fccd7f077ffa5a6d595aea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga142de52fd9fccd7f077ffa5a6d595aea">XCSITX_LCSTAT_VC0_ISR_MASK</a>&#160;&#160;&#160;(0x3&lt;&lt;8)</td></tr>
<tr class="memdesc:ga142de52fd9fccd7f077ffa5a6d595aea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC0 ISR.  <a href="#ga142de52fd9fccd7f077ffa5a6d595aea">More...</a><br/></td></tr>
<tr class="separator:ga142de52fd9fccd7f077ffa5a6d595aea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga987e9104d3d2c47d0a4241029df51d67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga987e9104d3d2c47d0a4241029df51d67">XCSITX_LCSTAT_VC1_ISR_MASK</a>&#160;&#160;&#160;(0x3&lt;&lt;10)</td></tr>
<tr class="memdesc:ga987e9104d3d2c47d0a4241029df51d67"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC1 ISR.  <a href="#ga987e9104d3d2c47d0a4241029df51d67">More...</a><br/></td></tr>
<tr class="separator:ga987e9104d3d2c47d0a4241029df51d67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga61d9538e0d010ffb6dc990475372fefb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga61d9538e0d010ffb6dc990475372fefb">XCSITX_LCSTAT_VC2_ISR_MASK</a>&#160;&#160;&#160;(0x3&lt;&lt;12)</td></tr>
<tr class="memdesc:ga61d9538e0d010ffb6dc990475372fefb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC2 ISR.  <a href="#ga61d9538e0d010ffb6dc990475372fefb">More...</a><br/></td></tr>
<tr class="separator:ga61d9538e0d010ffb6dc990475372fefb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae0bb66a7b93fa93e9ae7126a9e7c2397"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gae0bb66a7b93fa93e9ae7126a9e7c2397">XCSITX_LCSTAT_VC3_ISR_MASK</a>&#160;&#160;&#160;(0x3&lt;&lt;14)</td></tr>
<tr class="memdesc:gae0bb66a7b93fa93e9ae7126a9e7c2397"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC3 ISR.  <a href="#gae0bb66a7b93fa93e9ae7126a9e7c2397">More...</a><br/></td></tr>
<tr class="separator:gae0bb66a7b93fa93e9ae7126a9e7c2397"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga286313baf965deb60dec63793619c051"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga286313baf965deb60dec63793619c051">XCSITX_LCSTAT_VC0_ISR_OFFSET</a>&#160;&#160;&#160;(8)</td></tr>
<tr class="memdesc:ga286313baf965deb60dec63793619c051"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC0 ISR Offset.  <a href="#ga286313baf965deb60dec63793619c051">More...</a><br/></td></tr>
<tr class="separator:ga286313baf965deb60dec63793619c051"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf1a83a4df52d05590aa4f2f6e3c20a6c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gaf1a83a4df52d05590aa4f2f6e3c20a6c">XCSITX_LCSTAT_VC1_ISR_OFFSET</a>&#160;&#160;&#160;(10)</td></tr>
<tr class="memdesc:gaf1a83a4df52d05590aa4f2f6e3c20a6c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC1 ISR Offset.  <a href="#gaf1a83a4df52d05590aa4f2f6e3c20a6c">More...</a><br/></td></tr>
<tr class="separator:gaf1a83a4df52d05590aa4f2f6e3c20a6c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3ee9d8a174df41745968a05430f3a604"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga3ee9d8a174df41745968a05430f3a604">XCSITX_LCSTAT_VC2_ISR_OFFSET</a>&#160;&#160;&#160;(12)</td></tr>
<tr class="memdesc:ga3ee9d8a174df41745968a05430f3a604"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC2 ISR Offset.  <a href="#ga3ee9d8a174df41745968a05430f3a604">More...</a><br/></td></tr>
<tr class="separator:ga3ee9d8a174df41745968a05430f3a604"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga945d23526f204191f2d579e9169105d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga945d23526f204191f2d579e9169105d8">XCSITX_LCSTAT_VC3_ISR_OFFSET</a>&#160;&#160;&#160;(14)</td></tr>
<tr class="memdesc:ga945d23526f204191f2d579e9169105d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC3 ISR Offset.  <a href="#ga945d23526f204191f2d579e9169105d8">More...</a><br/></td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
BitMasks Short Packets</h2></td></tr>
<tr class="memitem:ga2edf8b9efa772fbbf6f9b59c8a62ae4e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2edf8b9efa772fbbf6f9b59c8a62ae4e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_SPKTR_DATA_MASK</b>&#160;&#160;&#160;0x00FFFF00 /* Short Packet byte0 and 1*/</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_SPKTR_DATA_SHIFT</b>&#160;&#160;&#160;8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_SPKTR_VC_MASK</b></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_SPKTR_VC_SHIFT</b>&#160;&#160;&#160;6</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_SPKTR_DT_MASK</b>&#160;&#160;&#160;0x0000003F /* Short Packet Data type*/</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_SPKTR_DT_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ga946323f75e230f56d7fc2a9640bd8ab1"></a>
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          <td class="memname">#define XCSI2TX_CCR_OFFSET&#160;&#160;&#160;0x00000000</td>
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<p>Core Configuration Register. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga8c4f599fd297b0b87b7b5028bc59a1a4">XCsi2Tx_SelfTest()</a>, and <a class="el" href="group__csi2tx.html#ga1f42ddbe8c72819877271b1e2b1b2f66">XCsi2Tx_SetLineCountForVC()</a>.</p>

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<a class="anchor" id="gaa5b4a62581a8f8fd68092c4d9f63c7fe"></a>
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          <td class="memname">#define XCSI2TX_DISABLE&#160;&#160;&#160;0</td>
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<p>Flag denoting disabling of CSI. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga7f455150c7e612ad6ddf0c052fff1f57">XCsi2Tx_Activate()</a>.</p>

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          <td class="memname">#define XCSI2TX_ENABLE&#160;&#160;&#160;1</td>
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<p>Flag denoting enabling of CSI. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga7f455150c7e612ad6ddf0c052fff1f57">XCsi2Tx_Activate()</a>.</p>

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<a class="anchor" id="gac6230fca4f7c1adbda9fe1552ef4b3d2"></a>
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          <td class="memname">#define XCSI2TX_GIER_GIE_MASK&#160;&#160;&#160;0x00000001</td>
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<p>Global Interrupt Enable bit. </p>

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</div>
<a class="anchor" id="ga933b9901187f38c45f7b70e52e3344a3"></a>
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          <td class="memname">#define XCSI2TX_GIER_GIE_SHIFT&#160;&#160;&#160;0</td>
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<p>Shift bits for Global Interrupt Enable. </p>

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<a class="anchor" id="ga9367d74644fe257d2d9ef283bf81d327"></a>
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          <td class="memname">#define XCSI2TX_GIER_OFFSET&#160;&#160;&#160;0x00000020</td>
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<p>Global Interrupt Register. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga874801fd63ef703d0b8ec36379b743a7">XCsi2Tx_Configure()</a>, and <a class="el" href="group__csi2tx.html#ga8c4f599fd297b0b87b7b5028bc59a1a4">XCsi2Tx_SelfTest()</a>.</p>

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</div>
<a class="anchor" id="ga4eee0cf8e8f3042e85023c2c9e614704"></a>
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          <td class="memname">#define XCSI2TX_GIER_RESET&#160;&#160;&#160;0</td>
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<p>Disable the Global Interrupts. </p>

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<a class="anchor" id="ga959e1d8eac158a90fdd7924124bf2bcc"></a>
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          <td class="memname">#define XCSI2TX_GIER_SET&#160;&#160;&#160;1</td>
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<p>Enable the Global Interrupts. </p>

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<a class="anchor" id="gac7a1f2d7c25c0f7238931c4941af0da8"></a>
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          <td class="memname">#define XCSI2TX_GSP_MASK&#160;&#160;&#160;0x00000001F</td>
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<p>Number of GSPs can be safely written to GSP FIFO, before it goes full. </p>

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<a class="anchor" id="gad58795e87b55fa4c2aea73405171341d"></a>
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          <td class="memname">#define XCSI2TX_H_</td>
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<p>Prevent circular inclusions by using protection macros. </p>

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</div>
<a class="anchor" id="ga8f58282f5d1917ec080b9b210aad48a6"></a>
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          <td class="memname">#define XCSI2TX_HW_H_</td>
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<p>Prevent circular inclusions by using protection macros. </p>

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</div>
<a class="anchor" id="ga2e9aa73ddca76ee93a3c18573a082f19"></a>
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          <td class="memname">#define XCSI2TX_IER_OFFSET&#160;&#160;&#160;0x00000028</td>
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<p>Interrupt Enable Register. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga3ff13690fd3d7cbb9ef1b0b8bf579235">XCsi2Tx_GetIntrEnable()</a>, <a class="el" href="group__csi2tx.html#gad54b9d4f661d683594d59fe7ab428962">XCsi2Tx_IntrDisable()</a>, <a class="el" href="group__csi2tx.html#ga2caa416a631b37b3414f3ebe811fb50e">XCsi2Tx_IntrEnable()</a>, and <a class="el" href="group__csi2tx.html#ga8c4f599fd297b0b87b7b5028bc59a1a4">XCsi2Tx_SelfTest()</a>.</p>

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<a class="anchor" id="gab2d607c7c70706cdb08326d2f9d35396"></a>
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          <td class="memname">#define XCSI2TX_ISR_OFFSET&#160;&#160;&#160;0x00000024</td>
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<p>Interrupt Status Register. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga40b9d2c4e3ac95c5a55c085ba0412304">XCsi2Tx_GetIntrStatus()</a>, <a class="el" href="group__csi2tx.html#ga60da0ba950424b0e90d2cf108eefed2c">XCsi2Tx_InterruptClear()</a>, and <a class="el" href="group__csi2tx.html#ga8c4f599fd297b0b87b7b5028bc59a1a4">XCsi2Tx_SelfTest()</a>.</p>

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<a class="anchor" id="ga71d1e5d100d088c2482482878f868530"></a>
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          <td class="memname">#define XCSI2TX_LINE_COUNT_VC0&#160;&#160;&#160;0x00000040</td>
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<p>Line Count for VC0. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga7aceee43ac75b5e2e7fb5c072e99543d">XCsi2Tx_GetLineCountForVC()</a>, and <a class="el" href="group__csi2tx.html#ga1f42ddbe8c72819877271b1e2b1b2f66">XCsi2Tx_SetLineCountForVC()</a>.</p>

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<a class="anchor" id="ga0416b10b41b6db1ec5a6ee91a79e7005"></a>
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          <td class="memname">#define XCSI2TX_LINE_COUNT_VC1&#160;&#160;&#160;0x00000044</td>
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<p>Line Count for VC1. </p>

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          <td class="memname">#define XCSI2TX_LINE_COUNT_VC2&#160;&#160;&#160;0x00000048</td>
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<p>Line Count for VC2. </p>

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<a class="anchor" id="ga23a3d797b27784997c641c8c8f0e984a"></a>
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          <td class="memname">#define XCSI2TX_LINE_COUNT_VC3&#160;&#160;&#160;0x0000004C</td>
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<p>Line Count for VC3. </p>

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          <td class="memname">#define XCSI2TX_MAX_LANES&#160;&#160;&#160;4</td>
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<p>Max Lanes supported by CSI. </p>

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          <td class="memname">#define XCSI2TX_MAX_VC&#160;&#160;&#160;4</td>
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<p>Max number of Virtual Channels. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga7aceee43ac75b5e2e7fb5c072e99543d">XCsi2Tx_GetLineCountForVC()</a>, and <a class="el" href="group__csi2tx.html#ga1f42ddbe8c72819877271b1e2b1b2f66">XCsi2Tx_SetLineCountForVC()</a>.</p>

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<a class="anchor" id="ga98c70dd97a33a24cd5a1d80f9fe9d902"></a>
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          <td class="memname">#define XCSI2TX_SPKTR_OFFSET&#160;&#160;&#160;0x00000030</td>
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<p>Generic Short Packet Entry. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#gad74fa52c21a09573d7838c8ec469cb82">XCsi2Tx_GetShortPacket()</a>, and <a class="el" href="group__csi2tx.html#ga8c4f599fd297b0b87b7b5028bc59a1a4">XCsi2Tx_SelfTest()</a>.</p>

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<a class="anchor" id="ga0044b3d448765635208740af525b7f8f"></a>
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          <td class="memname">#define XCSITX_LCSTAT_VC0_IER_MASK&#160;&#160;&#160;(1&lt;&lt;8)</td>
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<p>Line Count Status for VC0 IER. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#gad54b9d4f661d683594d59fe7ab428962">XCsi2Tx_IntrDisable()</a>, and <a class="el" href="group__csi2tx.html#ga2caa416a631b37b3414f3ebe811fb50e">XCsi2Tx_IntrEnable()</a>.</p>

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<a class="anchor" id="ga10a735a664b23493bbcfe038e7fc5090"></a>
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          <td class="memname">#define XCSITX_LCSTAT_VC0_IER_OFFSET&#160;&#160;&#160;(8)</td>
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<p>Line Count Status for VC0 IER Offset. </p>

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<a class="anchor" id="ga142de52fd9fccd7f077ffa5a6d595aea"></a>
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<p>Line Count Status for VC0 ISR. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga60da0ba950424b0e90d2cf108eefed2c">XCsi2Tx_InterruptClear()</a>, and <a class="el" href="group__csi2tx.html#gafc4a705bd3a295ac372fa02eb578af4d">XCsi2Tx_IntrHandler()</a>.</p>

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          <td class="memname">#define XCSITX_LCSTAT_VC0_ISR_OFFSET&#160;&#160;&#160;(8)</td>
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<p>Line Count Status for VC0 ISR Offset. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#gafc4a705bd3a295ac372fa02eb578af4d">XCsi2Tx_IntrHandler()</a>.</p>

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<p>Line Count Status for VC1 IER. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#gad54b9d4f661d683594d59fe7ab428962">XCsi2Tx_IntrDisable()</a>, and <a class="el" href="group__csi2tx.html#ga2caa416a631b37b3414f3ebe811fb50e">XCsi2Tx_IntrEnable()</a>.</p>

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          <td class="memname">#define XCSITX_LCSTAT_VC1_IER_OFFSET&#160;&#160;&#160;(10)</td>
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<p>Line Count Status for VC1 IER Offset. </p>

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          <td class="memname">#define XCSITX_LCSTAT_VC1_ISR_MASK&#160;&#160;&#160;(0x3&lt;&lt;10)</td>
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<p>Line Count Status for VC1 ISR. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga60da0ba950424b0e90d2cf108eefed2c">XCsi2Tx_InterruptClear()</a>, and <a class="el" href="group__csi2tx.html#gafc4a705bd3a295ac372fa02eb578af4d">XCsi2Tx_IntrHandler()</a>.</p>

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          <td class="memname">#define XCSITX_LCSTAT_VC1_ISR_OFFSET&#160;&#160;&#160;(10)</td>
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<p>Line Count Status for VC1 ISR Offset. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#gafc4a705bd3a295ac372fa02eb578af4d">XCsi2Tx_IntrHandler()</a>.</p>

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<p>Line Count Status for VC2 IER. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#gad54b9d4f661d683594d59fe7ab428962">XCsi2Tx_IntrDisable()</a>, and <a class="el" href="group__csi2tx.html#ga2caa416a631b37b3414f3ebe811fb50e">XCsi2Tx_IntrEnable()</a>.</p>

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          <td class="memname">#define XCSITX_LCSTAT_VC2_IER_OFFSET&#160;&#160;&#160;(12)</td>
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<p>Line Count Status for VC2 IER Offset. </p>

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<p>Line Count Status for VC2 ISR. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga60da0ba950424b0e90d2cf108eefed2c">XCsi2Tx_InterruptClear()</a>, and <a class="el" href="group__csi2tx.html#gafc4a705bd3a295ac372fa02eb578af4d">XCsi2Tx_IntrHandler()</a>.</p>

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          <td class="memname">#define XCSITX_LCSTAT_VC2_ISR_OFFSET&#160;&#160;&#160;(12)</td>
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<p>Line Count Status for VC2 ISR Offset. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#gafc4a705bd3a295ac372fa02eb578af4d">XCsi2Tx_IntrHandler()</a>.</p>

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          <td class="memname">#define XCSITX_LCSTAT_VC3_IER_MASK&#160;&#160;&#160;(1&lt;&lt;14)</td>
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<p>Line Count Status for VC3 IER. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#gad54b9d4f661d683594d59fe7ab428962">XCsi2Tx_IntrDisable()</a>, and <a class="el" href="group__csi2tx.html#ga2caa416a631b37b3414f3ebe811fb50e">XCsi2Tx_IntrEnable()</a>.</p>

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<p>Line Count Status for VC3 IER Offset. </p>

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          <td class="memname">#define XCSITX_LCSTAT_VC3_ISR_MASK&#160;&#160;&#160;(0x3&lt;&lt;14)</td>
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<p>Line Count Status for VC3 ISR. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga60da0ba950424b0e90d2cf108eefed2c">XCsi2Tx_InterruptClear()</a>, and <a class="el" href="group__csi2tx.html#gafc4a705bd3a295ac372fa02eb578af4d">XCsi2Tx_IntrHandler()</a>.</p>

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          <td class="memname">#define XCSITX_LCSTAT_VC3_ISR_OFFSET&#160;&#160;&#160;(14)</td>
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<p>Line Count Status for VC3 ISR Offset. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#gafc4a705bd3a295ac372fa02eb578af4d">XCsi2Tx_IntrHandler()</a>.</p>

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<h2 class="groupheader">Typedef Documentation</h2>
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          <td class="memname">typedef void(* XCsi2Tx_CallBack)(void *CallBackRef, u32 Mask)</td>
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<p>Callback type for all interrupts defined. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">CallBackRef</td><td>is a callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. </td></tr>
    <tr><td class="paramname">Mask</td><td>is a bit mask indicating the cause of the event. For current core version, this parameter is "OR" of 0 or more XCSI2TX_ISR_*_MASK constants defined in xcsi_hw.h.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

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<h2 class="groupheader">Enumeration Type Documentation</h2>
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          <td class="memname">enum <a class="el" href="group__csi2tx.html#ga46a443dfffd8f26578ebaf2a6139b4f3">XCsi2Tx_LCStatus</a></td>
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<p>This typedef defines the different errors codes for Line Count status for a Virtual Channel when Frame End Generation is enabled. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga46a443dfffd8f26578ebaf2a6139b4f3ae2ab61672a5cb405cae8c9770e7e7710"></a>XCSI2TX_LC_LESS_LINES</em>&nbsp;</td><td class="fielddoc">
<p>Less no of lines recvd. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga46a443dfffd8f26578ebaf2a6139b4f3a328322afaa225277614e41216fb55954"></a>XCSI2TX_LC_MORE_LINES</em>&nbsp;</td><td class="fielddoc">
<p>More no of lines recvd. </p>
</td></tr>
</table>

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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname">u32 Csi2TxSelfTestExample </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
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<p>This function checks if the Max Lane count from the generated file matches the value present in the protocol configuration register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>is the CSI2Tx Controller Device id.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if Lane Count match</li>
</ul>
</dd></dl>
<ul>
<li>XST_FAILURE if Lane Count don't match.</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csi2_tx___config.html#a3a98c112448388a88d774028e6621d5b">XCsi2Tx_Config::BaseAddr</a>, <a class="el" href="group__csi2tx.html#gac9ea3e1e3c6a8ecc2f5074caca2e4c6b">XCsi2Tx_CfgInitialize()</a>, <a class="el" href="group__csi2tx.html#gaf7407d28ef78a246a921b758e837dd90">XCsi2Tx_LookupConfig()</a>, and <a class="el" href="group__csi2tx.html#ga8c4f599fd297b0b87b7b5028bc59a1a4">XCsi2Tx_SelfTest()</a>.</p>

<p>Referenced by <a class="el" href="group__csi2tx.html#gae66f6b31b5ad750f1fe042a706a4e3d4">main()</a>.</p>

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          <td class="memname">int main </td>
          <td>(</td>
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<p>The entry point for this example. </p>
<p>It invokes the example function, and reports the execution status.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">None.</td><td></td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if example finishes successfully</li>
<li>XST_FAILURE if example fails.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__csi2tx.html#ga79fec6c8f14f43478aedaaaae040447e">Csi2TxSelfTestExample()</a>.</p>

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          <td class="memname">u32 XCsi2Tx_Activate </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Flag</em>&#160;</td>
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          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>Thsi function will enable/disable the IP Core to start processing. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_csi2_tx.html" title="The XCsi2Tx driver instance data. ">XCsi2Tx</a> instance to operate on. </td></tr>
    <tr><td class="paramname">Flag</td><td>will be used to indicate Enable or Disable action</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS on successful core enable or disable</li>
<li>XST_FAILURE if core disable times out.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csi2_tx.html#a76c9bc48780bdcef81faa31b4adafa6a">XCsi2Tx::IsReady</a>, <a class="el" href="group__csi2tx.html#gaa5b4a62581a8f8fd68092c4d9f63c7fe">XCSI2TX_DISABLE</a>, and <a class="el" href="group__csi2tx.html#ga22c9436f428a8fc799706fb133cb07e4">XCSI2TX_ENABLE</a>.</p>

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          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx___config.html">XCsi2Tx_Config</a> *&#160;</td>
          <td class="paramname"><em>CfgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>EffectiveAddr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Initialize the <a class="el" href="struct_x_csi2_tx.html" title="The XCsi2Tx driver instance data. ">XCsi2Tx</a> instance provided by the caller based on the given Config structure. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_csi2_tx.html" title="The XCsi2Tx driver instance data. ">XCsi2Tx</a> instance to operate on. </td></tr>
    <tr><td class="paramname">CfgPtr</td><td>is the device configuration structure containing information about a specific CSI. </td></tr>
    <tr><td class="paramname">EffectiveAddr</td><td>is the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS Initialization was successful.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csi2_tx___config.html#a3a98c112448388a88d774028e6621d5b">XCsi2Tx_Config::BaseAddr</a>, <a class="el" href="struct_x_csi2_tx.html#a1d7faad0e8b7a8b43c072367fdc89c63">XCsi2Tx::Config</a>, <a class="el" href="struct_x_csi2_tx.html#a3c86ae558202fcaa2f9b017c107e3bdc">XCsi2Tx::DPhyUlpsCallBack</a>, <a class="el" href="struct_x_csi2_tx.html#a5176cda99647b69325a0e2f2d93dd1f7">XCsi2Tx::GSPFIFOCallBack</a>, <a class="el" href="struct_x_csi2_tx.html#a8bd9e69f04cb904bc27cafca3ed1833f">XCsi2Tx::IncorrectLaneCallBack</a>, and <a class="el" href="struct_x_csi2_tx.html#a76c9bc48780bdcef81faa31b4adafa6a">XCsi2Tx::IsReady</a>.</p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga79fec6c8f14f43478aedaaaae040447e">Csi2TxSelfTestExample()</a>.</p>

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          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function will configure the core with proper number of Active Lanes. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_csi2_tx.html" title="The XCsi2Tx driver instance data. ">XCsi2Tx</a> instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS On configuring the core.</li>
<li>XST_FAILURE if active lanes not set correctly</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csi2_tx.html#a5a27c156112b7d2669ba4c5fc13a4fa5">XCsi2Tx::ActiveLanes</a>, <a class="el" href="struct_x_csi2_tx___config.html#a3a98c112448388a88d774028e6621d5b">XCsi2Tx_Config::BaseAddr</a>, <a class="el" href="struct_x_csi2_tx.html#a1d7faad0e8b7a8b43c072367fdc89c63">XCsi2Tx::Config</a>, <a class="el" href="struct_x_csi2_tx.html#a76c9bc48780bdcef81faa31b4adafa6a">XCsi2Tx::IsReady</a>, <a class="el" href="group__csi2tx.html#ga3ff13690fd3d7cbb9ef1b0b8bf579235">XCsi2Tx_GetIntrEnable()</a>, <a class="el" href="group__csi2tx.html#ga9367d74644fe257d2d9ef283bf81d327">XCSI2TX_GIER_OFFSET</a>, <a class="el" href="group__csi2tx.html#ga2caa416a631b37b3414f3ebe811fb50e">XCsi2Tx_IntrEnable()</a>, <a class="el" href="group__csi2tx.html#gac3002b53f14fc92a2f9dbd70466fb54f">XCsi2Tx_IsActiveLaneCountValid()</a>, and <a class="el" href="group__csi2tx.html#ga5a0232c79ceea489774863ec4cc3d9e0">XCsi2Tx_Reset()</a>.</p>

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          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function will get the interrupt mask set (enabled) in the CSI2 Tx core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the XCsi instance to operate on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Interrupt Mask with bits set for corresponding interrupt in Interrupt enable register</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p>References <a class="el" href="struct_x_csi2_tx___config.html#a3a98c112448388a88d774028e6621d5b">XCsi2Tx_Config::BaseAddr</a>, <a class="el" href="struct_x_csi2_tx.html#a1d7faad0e8b7a8b43c072367fdc89c63">XCsi2Tx::Config</a>, and <a class="el" href="group__csi2tx.html#ga2e9aa73ddca76ee93a3c18573a082f19">XCSI2TX_IER_OFFSET</a>.</p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga874801fd63ef703d0b8ec36379b743a7">XCsi2Tx_Configure()</a>.</p>

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          <td class="memname">u32 XCsi2Tx_GetIntrStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function will get the list of interrupts pending in the Interrupt Status Register of the CSI2 Tx core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the XCsi instance to operate on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Interrupt Mask with bits set for corresponding interrupt in Interrupt Status register</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p>References <a class="el" href="struct_x_csi2_tx___config.html#a3a98c112448388a88d774028e6621d5b">XCsi2Tx_Config::BaseAddr</a>, <a class="el" href="struct_x_csi2_tx.html#a1d7faad0e8b7a8b43c072367fdc89c63">XCsi2Tx::Config</a>, and <a class="el" href="group__csi2tx.html#gab2d607c7c70706cdb08326d2f9d35396">XCSI2TX_ISR_OFFSET</a>.</p>

<p>Referenced by <a class="el" href="group__csi2tx.html#gafc4a705bd3a295ac372fa02eb578af4d">XCsi2Tx_IntrHandler()</a>.</p>

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          <td class="memname">u32 XCsi2Tx_GetLineCountForVC </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>VC</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16 *&#160;</td>
          <td class="paramname"><em>LineCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function gets the Line Count for virtual Channel if Frame End Generation feature is enabled. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Subsystem instance to be worked on. </td></tr>
    <tr><td class="paramname">VC</td><td>is which Virtual channel to be configured for (0-3). </td></tr>
    <tr><td class="paramname">LineCount</td><td>is pointer to variable to be filled with line count for the Virtual channel</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_NO_FEATURE if Frame End generation is not enabled</li>
<li>XST_INVALID_PARAM if any param is invalid e.g. VC is always 0 to 3 and Line Count is 0 to 0xFFFF.</li>
<li>XST_SUCCESS otherwise</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csi2_tx___config.html#a3a98c112448388a88d774028e6621d5b">XCsi2Tx_Config::BaseAddr</a>, <a class="el" href="struct_x_csi2_tx.html#a1d7faad0e8b7a8b43c072367fdc89c63">XCsi2Tx::Config</a>, <a class="el" href="struct_x_csi2_tx___config.html#a661cd2b2d33ae733dffafdd736aaaaa2">XCsi2Tx_Config::FEGenEnabled</a>, <a class="el" href="group__csi2tx.html#ga71d1e5d100d088c2482482878f868530">XCSI2TX_LINE_COUNT_VC0</a>, and <a class="el" href="group__csi2tx.html#gaad964d27150f8888fdcde05db9f9ad18">XCSI2TX_MAX_VC</a>.</p>

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          <td class="memname">void XCsi2Tx_GetShortPacket </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx___s_pkt_data.html">XCsi2Tx_SPktData</a> *&#160;</td>
          <td class="paramname"><em>ShortPacketStruct</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function will get the short packet received in the FIFO from the Generic Short Packet Register and fill up the structure passed from caller. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_csi2_tx.html" title="The XCsi2Tx driver instance data. ">XCsi2Tx</a> instance to operate on </td></tr>
    <tr><td class="paramname">ShortPacketStruct</td><td>is going to be filled up by this function and returned to the caller.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>

<p>References <a class="el" href="struct_x_csi2_tx___config.html#a3a98c112448388a88d774028e6621d5b">XCsi2Tx_Config::BaseAddr</a>, <a class="el" href="struct_x_csi2_tx.html#a1d7faad0e8b7a8b43c072367fdc89c63">XCsi2Tx::Config</a>, <a class="el" href="struct_x_csi2_tx___s_pkt_data.html#ae7eaab1966c80ad19b6b2c4de7192921">XCsi2Tx_SPktData::Data</a>, <a class="el" href="struct_x_csi2_tx___s_pkt_data.html#aeac6271aded8b7441de5769f4e01a116">XCsi2Tx_SPktData::DataType</a>, <a class="el" href="struct_x_csi2_tx___s_pkt_data.html#a3bf0c843bd9e0088989ea6ea90b8b6af">XCsi2Tx_SPktData::VirtualChannel</a>, and <a class="el" href="group__csi2tx.html#ga98c70dd97a33a24cd5a1d80f9fe9d902">XCSI2TX_SPKTR_OFFSET</a>.</p>

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          <td class="memname">void XCsi2Tx_InterruptClear </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function will clear the interrupts set in the Interrupt Status Register of the CSI2 Tx core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the XCsi instance to operate on </td></tr>
    <tr><td class="paramname">Mask</td><td>is Interrupt Mask with bits set for corresponding interrupt to be cleared in the Interrupt Status register</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p>References <a class="el" href="struct_x_csi2_tx___config.html#a3a98c112448388a88d774028e6621d5b">XCsi2Tx_Config::BaseAddr</a>, <a class="el" href="struct_x_csi2_tx.html#a1d7faad0e8b7a8b43c072367fdc89c63">XCsi2Tx::Config</a>, <a class="el" href="struct_x_csi2_tx___config.html#a661cd2b2d33ae733dffafdd736aaaaa2">XCsi2Tx_Config::FEGenEnabled</a>, <a class="el" href="group__csi2tx.html#gab2d607c7c70706cdb08326d2f9d35396">XCSI2TX_ISR_OFFSET</a>, <a class="el" href="group__csi2tx.html#ga142de52fd9fccd7f077ffa5a6d595aea">XCSITX_LCSTAT_VC0_ISR_MASK</a>, <a class="el" href="group__csi2tx.html#ga987e9104d3d2c47d0a4241029df51d67">XCSITX_LCSTAT_VC1_ISR_MASK</a>, <a class="el" href="group__csi2tx.html#ga61d9538e0d010ffb6dc990475372fefb">XCSITX_LCSTAT_VC2_ISR_MASK</a>, and <a class="el" href="group__csi2tx.html#gae0bb66a7b93fa93e9ae7126a9e7c2397">XCSITX_LCSTAT_VC3_ISR_MASK</a>.</p>

<p>Referenced by <a class="el" href="group__csi2tx.html#gafc4a705bd3a295ac372fa02eb578af4d">XCsi2Tx_IntrHandler()</a>.</p>

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          <td class="memname">void XCsi2Tx_IntrDisable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function will disable the interrupts present in the interrupt mask passed onto the function. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the XCsi instance to operate on </td></tr>
    <tr><td class="paramname">Mask</td><td>is the interrupt mask which need to be enabled in core</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p>References <a class="el" href="struct_x_csi2_tx___config.html#a3a98c112448388a88d774028e6621d5b">XCsi2Tx_Config::BaseAddr</a>, <a class="el" href="struct_x_csi2_tx.html#a1d7faad0e8b7a8b43c072367fdc89c63">XCsi2Tx::Config</a>, <a class="el" href="struct_x_csi2_tx___config.html#a661cd2b2d33ae733dffafdd736aaaaa2">XCsi2Tx_Config::FEGenEnabled</a>, <a class="el" href="group__csi2tx.html#ga2e9aa73ddca76ee93a3c18573a082f19">XCSI2TX_IER_OFFSET</a>, <a class="el" href="group__csi2tx.html#ga0044b3d448765635208740af525b7f8f">XCSITX_LCSTAT_VC0_IER_MASK</a>, <a class="el" href="group__csi2tx.html#ga5a70be53ce33122f5cc5d0f4d0450bf6">XCSITX_LCSTAT_VC1_IER_MASK</a>, <a class="el" href="group__csi2tx.html#gaaffcbe2e0effcbd2ff9806e9e28ebf26">XCSITX_LCSTAT_VC2_IER_MASK</a>, and <a class="el" href="group__csi2tx.html#ga0bd1beb0451ef2e16f517a7933069e68">XCSITX_LCSTAT_VC3_IER_MASK</a>.</p>

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          <td class="memname">void XCsi2Tx_IntrEnable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function will enable the interrupts present in the interrupt mask passed onto the function. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the XCsi instance to operate on </td></tr>
    <tr><td class="paramname">Mask</td><td>is the interrupt mask which need to be enabled in core</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p>References <a class="el" href="struct_x_csi2_tx___config.html#a3a98c112448388a88d774028e6621d5b">XCsi2Tx_Config::BaseAddr</a>, <a class="el" href="struct_x_csi2_tx.html#a1d7faad0e8b7a8b43c072367fdc89c63">XCsi2Tx::Config</a>, <a class="el" href="struct_x_csi2_tx___config.html#a661cd2b2d33ae733dffafdd736aaaaa2">XCsi2Tx_Config::FEGenEnabled</a>, <a class="el" href="group__csi2tx.html#ga2e9aa73ddca76ee93a3c18573a082f19">XCSI2TX_IER_OFFSET</a>, <a class="el" href="group__csi2tx.html#ga0044b3d448765635208740af525b7f8f">XCSITX_LCSTAT_VC0_IER_MASK</a>, <a class="el" href="group__csi2tx.html#ga5a70be53ce33122f5cc5d0f4d0450bf6">XCSITX_LCSTAT_VC1_IER_MASK</a>, <a class="el" href="group__csi2tx.html#gaaffcbe2e0effcbd2ff9806e9e28ebf26">XCSITX_LCSTAT_VC2_IER_MASK</a>, and <a class="el" href="group__csi2tx.html#ga0bd1beb0451ef2e16f517a7933069e68">XCSITX_LCSTAT_VC3_IER_MASK</a>.</p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga874801fd63ef703d0b8ec36379b743a7">XCsi2Tx_Configure()</a>.</p>

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          <td class="memname">void XCsi2Tx_IntrHandler </td>
          <td>(</td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function is the interrupt handler for the CSI2 Tx core. </p>
<p>This handler reads the pending interrupt from the Interrupt Status register, determines the source of the interrupts and calls the respective callbacks for the interrupts that are enabled in Interrupt Enable register, and finally clears the interrupts.</p>
<p>The application is responsible for connecting this function to the interrupt system. Application beyond this core is also responsible for providing callbacks to handle interrupts and installing the callbacks using <a class="el" href="group__csi2tx.html#ga4dd6f019a905c50bfa662e9823cf5b00" title="This routine installs an asynchronous callback function for the given HandlerType: ...">XCsi2Tx_SetCallBack()</a> during initialization phase.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_csi2_tx.html" title="The XCsi2Tx driver instance data. ">XCsi2Tx</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Interrupt should be enabled to execute interrupt handler. </dd></dl>

<p>References <a class="el" href="struct_x_csi2_tx.html#a1d7faad0e8b7a8b43c072367fdc89c63">XCsi2Tx::Config</a>, <a class="el" href="struct_x_csi2_tx.html#a3c86ae558202fcaa2f9b017c107e3bdc">XCsi2Tx::DPhyUlpsCallBack</a>, <a class="el" href="struct_x_csi2_tx.html#a8d43562511a5a9f0f29096f90be51afb">XCsi2Tx::DPhyUlpsRef</a>, <a class="el" href="struct_x_csi2_tx___config.html#a661cd2b2d33ae733dffafdd736aaaaa2">XCsi2Tx_Config::FEGenEnabled</a>, <a class="el" href="struct_x_csi2_tx.html#a5176cda99647b69325a0e2f2d93dd1f7">XCsi2Tx::GSPFIFOCallBack</a>, <a class="el" href="struct_x_csi2_tx.html#a8bd9e69f04cb904bc27cafca3ed1833f">XCsi2Tx::IncorrectLaneCallBack</a>, <a class="el" href="struct_x_csi2_tx.html#a804d76480f983c4a0b2826eeb3d6199a">XCsi2Tx::IncorrectLaneRef</a>, <a class="el" href="struct_x_csi2_tx.html#a76c9bc48780bdcef81faa31b4adafa6a">XCsi2Tx::IsReady</a>, <a class="el" href="struct_x_csi2_tx.html#ac8e54aecadd550abe63cf1b19af48d0e">XCsi2Tx::LCErrVC0Ref</a>, <a class="el" href="struct_x_csi2_tx.html#a0fc393310d82667aa783ed40bfd12d76">XCsi2Tx::LCErrVC1Ref</a>, <a class="el" href="struct_x_csi2_tx.html#a459ea7918c3bf9a1a8b09b451722e6cb">XCsi2Tx::LCErrVC2Ref</a>, <a class="el" href="struct_x_csi2_tx.html#a4032f85a26722120464fcc6d7e63b01c">XCsi2Tx::LCErrVC3Ref</a>, <a class="el" href="struct_x_csi2_tx.html#a6b11d3ca677d64d2e43b21107e1b17ee">XCsi2Tx::LineBufferRef</a>, <a class="el" href="struct_x_csi2_tx.html#aeaa044cf9957f0c3b1097f3c15db3227">XCsi2Tx::UnderrunPixelRef</a>, <a class="el" href="group__csi2tx.html#ga40b9d2c4e3ac95c5a55c085ba0412304">XCsi2Tx_GetIntrStatus()</a>, <a class="el" href="group__csi2tx.html#ga60da0ba950424b0e90d2cf108eefed2c">XCsi2Tx_InterruptClear()</a>, <a class="el" href="group__csi2tx.html#gga46a443dfffd8f26578ebaf2a6139b4f3ae2ab61672a5cb405cae8c9770e7e7710">XCSI2TX_LC_LESS_LINES</a>, <a class="el" href="group__csi2tx.html#gga46a443dfffd8f26578ebaf2a6139b4f3a328322afaa225277614e41216fb55954">XCSI2TX_LC_MORE_LINES</a>, <a class="el" href="group__csi2tx.html#ga142de52fd9fccd7f077ffa5a6d595aea">XCSITX_LCSTAT_VC0_ISR_MASK</a>, <a class="el" href="group__csi2tx.html#ga286313baf965deb60dec63793619c051">XCSITX_LCSTAT_VC0_ISR_OFFSET</a>, <a class="el" href="group__csi2tx.html#ga987e9104d3d2c47d0a4241029df51d67">XCSITX_LCSTAT_VC1_ISR_MASK</a>, <a class="el" href="group__csi2tx.html#gaf1a83a4df52d05590aa4f2f6e3c20a6c">XCSITX_LCSTAT_VC1_ISR_OFFSET</a>, <a class="el" href="group__csi2tx.html#ga61d9538e0d010ffb6dc990475372fefb">XCSITX_LCSTAT_VC2_ISR_MASK</a>, <a class="el" href="group__csi2tx.html#ga3ee9d8a174df41745968a05430f3a604">XCSITX_LCSTAT_VC2_ISR_OFFSET</a>, <a class="el" href="group__csi2tx.html#gae0bb66a7b93fa93e9ae7126a9e7c2397">XCSITX_LCSTAT_VC3_ISR_MASK</a>, and <a class="el" href="group__csi2tx.html#ga945d23526f204191f2d579e9169105d8">XCSITX_LCSTAT_VC3_ISR_OFFSET</a>.</p>

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          <td class="memname">u8 XCsi2Tx_IsActiveLaneCountValid </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>ActiveLanesCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function checks the validity of the active lanes parameter. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Subsystem instance to be worked on. </td></tr>
    <tr><td class="paramname">ActiveLanesCount</td><td>is the lane count to check if valid.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>1 if specified Active Lanes is valid.</li>
<li>0 otherwise, if the Active Lanes specified isn't valid as per spec and design.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csi2_tx.html#a1d7faad0e8b7a8b43c072367fdc89c63">XCsi2Tx::Config</a>, and <a class="el" href="struct_x_csi2_tx___config.html#a81490985967772106c88ddf719652d37">XCsi2Tx_Config::MaxLanesPresent</a>.</p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga874801fd63ef703d0b8ec36379b743a7">XCsi2Tx_Configure()</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_csi2_tx___config.html">XCsi2Tx_Config</a> * XCsi2Tx_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
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<p>Look up the hardware configuration for a device instance. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>is the unique device ID of the device to lookup for</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The reference to the configuration record in the configuration table (in xcsi2tx_g.c) corresponding to the Device ID or if not found,a NULL pointer is returned.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga79fec6c8f14f43478aedaaaae040447e">Csi2TxSelfTestExample()</a>.</p>

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          <td class="memname">u32 XCsi2Tx_Reset </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function will do a reset of the IP. </p>
<p>This will reset the values of all regiters except Core Config and Protocol Config registers.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_csi2_tx.html" title="The XCsi2Tx driver instance data. ">XCsi2Tx</a> instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS On proper reset.</li>
<li>XST_FAILURE on timeout and core being stuck in reset</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga874801fd63ef703d0b8ec36379b743a7">XCsi2Tx_Configure()</a>, and <a class="el" href="group__csi2tx.html#ga8c4f599fd297b0b87b7b5028bc59a1a4">XCsi2Tx_SelfTest()</a>.</p>

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          <td class="memname">u32 XCsi2Tx_SelfTest </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>Runs a self-test on the driver/device. </p>
<p>This test checks if the LaneCount present in register matches the one from the generated file.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XCsi instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if self-test was successful</li>
<li>XST_FAILURE if the read value was not equal to _g.c file</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p>References <a class="el" href="struct_x_csi2_tx___config.html#a3a98c112448388a88d774028e6621d5b">XCsi2Tx_Config::BaseAddr</a>, <a class="el" href="struct_x_csi2_tx.html#a1d7faad0e8b7a8b43c072367fdc89c63">XCsi2Tx::Config</a>, <a class="el" href="struct_x_csi2_tx.html#a76c9bc48780bdcef81faa31b4adafa6a">XCsi2Tx::IsReady</a>, <a class="el" href="struct_x_csi2_tx___config.html#a81490985967772106c88ddf719652d37">XCsi2Tx_Config::MaxLanesPresent</a>, <a class="el" href="group__csi2tx.html#ga946323f75e230f56d7fc2a9640bd8ab1">XCSI2TX_CCR_OFFSET</a>, <a class="el" href="group__csi2tx.html#ga9367d74644fe257d2d9ef283bf81d327">XCSI2TX_GIER_OFFSET</a>, <a class="el" href="group__csi2tx.html#ga2e9aa73ddca76ee93a3c18573a082f19">XCSI2TX_IER_OFFSET</a>, <a class="el" href="group__csi2tx.html#gab2d607c7c70706cdb08326d2f9d35396">XCSI2TX_ISR_OFFSET</a>, <a class="el" href="group__csi2tx.html#ga5a0232c79ceea489774863ec4cc3d9e0">XCsi2Tx_Reset()</a>, and <a class="el" href="group__csi2tx.html#ga98c70dd97a33a24cd5a1d80f9fe9d902">XCSI2TX_SPKTR_OFFSET</a>.</p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga79fec6c8f14f43478aedaaaae040447e">Csi2TxSelfTestExample()</a>.</p>

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          <td class="memname">int XCsi2Tx_SetCallBack </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>HandleType</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>Callbackfunc</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>Callbackref</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This routine installs an asynchronous callback function for the given HandlerType: </p>
<pre>
HandlerType                             Callback Function Type
----------------------------  --------------------------------------------
(XCSI2TX_HANDLER_WRG_LANE)              IncorrectLaneCallBack
(XCSI2TX_HANDLER_GSPFIFO_FULL)  GSPFIFOCallBack
(XCSI2TX_HANDLER_ULPS)          DPhyUlpsCallBack
(XCSI2TX_HANDLER_LINEBUF_FULL)  LineBufferCallBack
(XCSI2TX_HANDLER_WRG_DATATYPE)  WrgDataTypeCallBack
(XCSI2TX_HANDLER_UNDERRUN_PIXEL)        UnderrunPixelCallBack
(XCSI2TX_HANDLER_LCERRVC0)              LineCountErrVC0
(XCSI2TX_HANDLER_LCERRVC1)              LineCountErrVC1
(XCSI2TX_HANDLER_LCERRVC2)              LineCountErrVC2
(XCSI2TX_HANDLER_LCERRVC3)              LineCountErrVC3
</pre><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_csi2_tx.html" title="The XCsi2Tx driver instance data. ">XCsi2Tx</a> instance to operate on </td></tr>
    <tr><td class="paramname">HandleType</td><td>is the type of call back to be registered. </td></tr>
    <tr><td class="paramname">Callbackfunc</td><td>is the pointer to a call back funtion which is called when a particular event occurs. </td></tr>
    <tr><td class="paramname">Callbackref</td><td>is a void pointer to data to be referenced to by the Callbackfunc</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS when handler is installed.</li>
<li>XST_INVALID_PARAM when HandlerType is invalid.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Invoking this function for a handler that already has been installed replaces it with the new handler. </dd></dl>

<p>References <a class="el" href="struct_x_csi2_tx.html#a3c86ae558202fcaa2f9b017c107e3bdc">XCsi2Tx::DPhyUlpsCallBack</a>, <a class="el" href="struct_x_csi2_tx.html#a8d43562511a5a9f0f29096f90be51afb">XCsi2Tx::DPhyUlpsRef</a>, <a class="el" href="struct_x_csi2_tx.html#a5176cda99647b69325a0e2f2d93dd1f7">XCsi2Tx::GSPFIFOCallBack</a>, <a class="el" href="struct_x_csi2_tx.html#a8bd9e69f04cb904bc27cafca3ed1833f">XCsi2Tx::IncorrectLaneCallBack</a>, <a class="el" href="struct_x_csi2_tx.html#a804d76480f983c4a0b2826eeb3d6199a">XCsi2Tx::IncorrectLaneRef</a>, <a class="el" href="struct_x_csi2_tx.html#a76c9bc48780bdcef81faa31b4adafa6a">XCsi2Tx::IsReady</a>, <a class="el" href="struct_x_csi2_tx.html#ac8e54aecadd550abe63cf1b19af48d0e">XCsi2Tx::LCErrVC0Ref</a>, <a class="el" href="struct_x_csi2_tx.html#a0fc393310d82667aa783ed40bfd12d76">XCsi2Tx::LCErrVC1Ref</a>, <a class="el" href="struct_x_csi2_tx.html#a459ea7918c3bf9a1a8b09b451722e6cb">XCsi2Tx::LCErrVC2Ref</a>, <a class="el" href="struct_x_csi2_tx.html#a4032f85a26722120464fcc6d7e63b01c">XCsi2Tx::LCErrVC3Ref</a>, <a class="el" href="struct_x_csi2_tx.html#a6b11d3ca677d64d2e43b21107e1b17ee">XCsi2Tx::LineBufferRef</a>, and <a class="el" href="struct_x_csi2_tx.html#aeaa044cf9957f0c3b1097f3c15db3227">XCsi2Tx::UnderrunPixelRef</a>.</p>

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          <td class="memname">u32 XCsi2Tx_SetLineCountForVC </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csi2_tx.html">XCsi2Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>VC</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>LineCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function sets the Line Count for virtual Channel if Frame End Generation feature is enabled. </p>
<p>This is to be called before starting the core.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Subsystem instance to be worked on. </td></tr>
    <tr><td class="paramname">VC</td><td>is which Virtual channel to be configured for (0-3). </td></tr>
    <tr><td class="paramname">LineCount</td><td>is valid line count for the Virtual channel.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_NO_FEATURE if Frame End generation is not enabled</li>
<li>XST_INVALID_PARAM if any param is invalid e.g. VC is always 0 to 3 and Line Count is 0 to 0xFFFF.</li>
<li>XST_FAILURE in case the core is already running.</li>
<li>XST_SUCCESS otherwise</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csi2_tx___config.html#a3a98c112448388a88d774028e6621d5b">XCsi2Tx_Config::BaseAddr</a>, <a class="el" href="struct_x_csi2_tx.html#a1d7faad0e8b7a8b43c072367fdc89c63">XCsi2Tx::Config</a>, <a class="el" href="struct_x_csi2_tx___config.html#a661cd2b2d33ae733dffafdd736aaaaa2">XCsi2Tx_Config::FEGenEnabled</a>, <a class="el" href="group__csi2tx.html#ga946323f75e230f56d7fc2a9640bd8ab1">XCSI2TX_CCR_OFFSET</a>, <a class="el" href="group__csi2tx.html#ga71d1e5d100d088c2482482878f868530">XCSI2TX_LINE_COUNT_VC0</a>, and <a class="el" href="group__csi2tx.html#gaad964d27150f8888fdcde05db9f9ad18">XCSI2TX_MAX_VC</a>.</p>

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